Metal Wiring and Method for Forming the Same

ABSTRACT

A metal wiring and method for forming the same are provided. A first conductive layer is formed on a semiconductor substrate, and an insulating layer is formed on the first conductive layer. A via and a trench are formed in the insulating layer, and a second conductive layer is formed by burying metal in the via and the trench. The insulating layer also includes materials with a low dielectric constant filled in second vias

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims the benefit under 35 U.S.C. §119 ofKorean Patent Application No. 10-2006-0082088, filed Aug. 29, 2006,which is hereby incorporated by reference in its entirety.

BACKGROUND

Copper is often used as interconnection material in integrated circuits.When forming a metal wiring of a semiconductor device, a thin film ofcopper (Cu) can improve the reliability of the semiconductor device ascompared to using aluminum (Al). Copper has a higher melting point thanaluminum and can improve the speed of signal transfer since it has a lowspecific resistance.

However, the etching characteristics of copper are very poor.Accordingly, a dual damascene process has been applied when usingcopper.

BRIEF SUMMARY

Embodiments of the present invention provide a metal wiring and a methodfor forming the same. The metal wiring has a low dielectric constant andexcellent mechanical strength

A method for forming a metal wiring according to an embodiment includes:forming a first conductive layer on a semiconductor substrate; formingan insulating layer on the first conductive layer; forming a via and atrench by selectively removing a portion of the insulating layer;forming a second conductive layer by burying metal in the via and thetrench; forming a plurality of vias in the insulating material; andfilling in the plurality of vias with materials that have a lowdielectric constant.

A metal wiring according to an embodiment includes: a first conductivelayer formed on a semiconductor substrate; an insulating layer formed onthe first conductive layer; a second conductive layer formed in theinsulating layer; and materials with a low dielectric constant in theinsulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 5 are cross-sectional views showing a method for forming ametal wiring according to an embodiment of the present invention.

DETAILED DESCRIPTION

When the terms “on” or “over” are used herein, when referring to layers,regions, patterns, or structures, it is understood that the layer,region, pattern or structure can be directly on another layer orstructure, or intervening layers, regions, patterns, or structures mayalso be present. When the terms “under” or “below” are used herein, whenreferring to layers, regions, patterns, or structures, it is understoodthat the layer, region, pattern or structure can be directly under theother layer or structure, or intervening layers, regions, patterns, orstructures may also be present.

Referring to FIG. 1, a first insulating layer 200 and a first conductivelayer 202 can be formed on a semiconductor substrate (not shown). Asecond insulating layer 204 can be formed on the first conductive layer202. A first photoresist 206 for a photo process can be applied on thesecond insulating layer 204. In an embodiment, the second insulatinglayer 204 is formed of fluoro-silicate glass (FSG). In an alternativeembodiment, the second insulating layer 204 can be formed of blackdiamond (BD). BD has a lower dielectric constant than FSG.

Referring to FIG. 2, a first photoresist pattern 206′ can be formed by aphoto process. Then, the second insulating layer 204 can be etched usingthe photoresist pattern 206′ as a mask, thereby forming a first viaregion 208.

Referring to FIG. 3, after the first photoresist pattern 206′ isremoved, a second photoresist (not shown) can be applied to the uppersurface of the substrate, and a photo process can be performed on thesecond photoresist, thereby forming a second photoresist pattern 210.Then, the second insulating layer 204 can be etched again using thesecond photoresist pattern 210 as a mask to form a trench wiring region212.

Referring to FIG. 4, the second photoresist pattern 210 patterned can beremoved. Then, an electro chemical plating (ECP) process can beperformed to form a second conductive layer 214 in the first via region208 and the trench wiring region 212. In an embodiment, the secondconductive layer can be copper. In a further embodiment, the secondconductive layer can include a barrier metal.

The second insulating layer 204′ can be etched again using the thirdphotoresist pattern (not shown) as a mask to form second via regions216.

Referring to FIG. 5, a spin coating method or a high density plasma(HDP) deposition method can also be performed to form low-K dielectricmaterials 218 in a plurality of second via regions 216 in the secondinsulating layer 204′.

Materials with a low dielectric constant can be formed in the second viaregions 216 of the second insulating layer 204′.

In many embodiments, the low-K dielectric materials 218 can be oxidationmaterials having excellent mechanical strength. In an embodiment, thelow-K dielectric materials 218 can be BLACK DIAMOND (BD), which can havea lower dielectric constant than the second insulating layer 204.

In an embodiment, the BD 218 can be filled into the second via regions216 by a spin coating method. In an alternative embodiment, the BD 218can be filled into the second via regions 216 by a high density plasma(HDP) deposition method, In an embodiment, the dielectric constant ofthe BD 218 used to fill the second via regions 216 is from about 2.6 toabout 3.1.

In embodiments in which the second insulating layer is formed of FSG,the dielectric constant of the second insulating layer is from about 3.4to about 3.8. Thus, using BD 218 to fill in the second via regions helpsmake it possible to provide mechanical strength and maintain a low-Kdielectric.

In embodiments in which the second insulating layer 204 is formed of BD,the materials used to fill in the second via regions 216 can be FSG.

In an embodiment, FSG can fill in the second via regions by a spincoating method. In an alternative embodiment, FSG can fill in the secondvia regions by a HDP deposition method. In an embodiment, the dielectricconstant of the FSG is from about 3.4 to about 3.8.

When formed of BD, the dielectric constant of the second insulatinglayer is from about 2.6 to about 3.1. Thus, using FSG having adielectric constant of from about 3.4 to about 3.8 to fill in the secondvia regions helps make it possible to provide mechanical strength, whilemaintaining the low-K dielectric.

The second conductive layer 214 can be present only in the first viaregion 208 and the trench wiring region 212 to form a via contactingpart 220 and a wiring part 222.

Embodiments of the present invention allow for the formation of a viaregion on an insulating layer in a dual damascene pattern. The use of BDor FSG provide excellent mechanical strength and a low dielectricconstant within the via region. This maintains the low dielectricconstant of porous materials while simultaneously securing mechanicalstrength.

Any reference in this specification to “one embodiment,” “anembodiment,” “example embodiment,” etc., means that a particularfeature, structure, or characteristic described in connection with theembodiment is included in at least one embodiment of the invention. Theappearances of such phrases in various places in the specification arenot necessarily all referring to the same embodiment. Further, when aparticular feature, structure, or characteristic is described inconnection with any embodiment, it is submitted that it is within thepurview of one skilled in the art to effect such feature, structure, orcharacteristic in connection with other ones of the embodiments.

Although embodiments have been described with reference to a number ofillustrative embodiments thereof, it should be understood that numerousother modifications and embodiments can be devised by those skilled inthe art that will fall within the spirit and scope of the principles ofthis disclosure. More particularly, various variations and modificationsare possible in the component parts and/or arrangements of the subjectcombination arrangement within the scope of the disclosure, the drawingsand the appended claims. In addition to variations and modifications inthe component parts and/or arrangements, alternative uses will also beapparent to those skilled in the art.

1. A method for forming a metal wiring, comprising: forming a firstconductive layer on a semiconductor substrate; forming an insulatinglayer on the first conductive layer; forming a first via and a trench inthe second insulating layer; forming a second conductive layer in thefirst via and the trench; and forming a plurality of second vias in theinsulating layer adjacent the first via and the trench; and filling eachof the second vias with an oxidation material having a low-K dielectric.2. The method according to claim 1, wherein the insulating layercomprises fluoro-silicate glass.
 3. The method according to claim 2,wherein the oxidation material having a low-K dielectric comprises BLACKDIAMOND.
 4. The method according to claim 3, wherein the dielectricconstant of the insulating layer is from about 3.4 to about 3.8, andwherein the dielectric constant of the oxidation material having a low-Kdielectric is from about 2.6 to about 3.1.
 5. The method according toclaim 3, wherein filling each of the second vias with the oxidationmaterial having a low-K dielectric comprises performing a spin coatingmethod.
 6. The method according to claim 3, wherein filling each of thesecond vias with the oxidation material having a low-K dielectriccomprises performing a high density plasma deposition method.
 7. Themethod according to claim 1, wherein the insulating layer comprisesBLACK DIAMOND.
 8. The method according to claim 7, wherein the oxidationmaterial having a low-K dielectric comprises fluoro-silicate glass. 9.The method according to claim 8, wherein the dielectric constant of theinsulating layer is from about 2.6 to about 3.1, and wherein thedielectric constant of the oxidation material having a low-K dielectricis from about 3.4 to about 3.8.
 10. The method according to claim 8,wherein filling each of the second vias with the oxidation materialhaving a low-K dielectric comprises performing a spin coating method.11. The method according to claim 8, wherein filling each of the secondvias with the oxidation material having a low-K dielectric comprisesperforming a high density plasma deposition method.
 12. The methodaccording to claim 1, wherein forming the second conductive layer in thefirst via and the trench comprises performing an electro-chemicalplating (ECP) process.
 13. The method according to claim 1, wherein themetal comprises copper.
 14. A metal wiring, comprising: a firstconductive layer on a semiconductor substrate; an insulating layer onthe first conductive layer, the insulating layer comprising a first via,a trench on the first via, and a plurality of second vias adjacent thetrench; a second conductive layer formed comprising metal in the firstvia and the trench of the insulating layer; and a low-K dielectricoxidation material in the plurality of second vias of the insulatinglayer.
 15. The metal wiring according to claim 14, wherein theinsulating layer comprises fluoro-silicate glass.
 16. The metal wiringaccording to claim 15, wherein the low-K dielectric oxidation metalcomprises BLACK DIAMOND.
 17. The metal wiring according to claim 16,wherein the dielectric constant of the insulating layer is from about3.4 to about 3.8, and wherein the dielectric constant of the low-Kdielectric oxidation material is from about 2.6 to about 3.1.
 18. Themetal wiring according to claim 14, wherein the insulating layercomprises BLACK DIAMOND.
 19. The metal wiring according to claim 18,wherein the low-K dielectric oxidation material comprisesfluoro-silicate glass.
 20. The metal wiring according to claim 14,wherein the metal comprises copper.